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@article{204466,
        author = {Kurma Yesebu Babu and Buddi Bhuvana Sai and Gummadidala Lokesh and D.N.D. Chandra Shekar},
        title = {Implementation and Functional Verification of an Asynchronous FIFO with Gray Code Pointer Synchronization on Nexys A7 FPGA},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {2666-2675},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=204466},
        abstract = {This paper presents the implementation and functional verification of a parameterized asynchronous First-In First-Out (FIFO) buffer designed for reliable data communication across independent clock domains. Clock Domain Crossing (CDC) is a persistent challenge in modern digital system design; improper handling of multi-bit transfers across asynchronous boundaries frequently causes metastability and data corruption. The proposed design employs gray code-encoded read and write pointers, which guarantee single-bit transitions between consecutive counter values, thereby minimizing synchronization hazards. Pointer information is transferred between domains through dual flip-flop synchronizer chains. The system is partitioned into five synthesizable Verilog HDL modules: a top-level controller, a dual-port FIFO memory, a write pointer handler with full-flag generation, a read pointer handler with empty-flag detection, and a two-stage synchronizer. The complete design was synthesized, placed, and routed using Xilinx Vivado 2023.1, targeting the Artix-7 XC7A100T device on a Digilent Nexys A7 development board. Functional correctness was validated through a self-checking SystemVerilog testbench that applied randomized stimuli at asymmetric clock frequencies of 50 MHz (write) and approximately 14.3 MHz (read). All 30 test transactions produced matching write and read data, confirming zero data loss and correct flag behaviour under sustained asynchronous operation. Pin-assignment results from Vivado, RTL schematics, and board-level observations are presented.},
        keywords = {Asynchronous FIFO, Clock Domain Crossing, Gray Code Synchronization, Metastability, FPGA Implementation, Nexys A7, Verilog HDL},
        month = {June},
        }