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@article{208035,
author = {Aniket Kumar and Sugandha Agarwal},
title = {Implementation and Performance Analysis of Vedic Multipliers on Nanoscale Power-Efficient FPGA Architectures},
journal = {International Journal of Innovative Research in Technology},
year = {2026},
volume = {13},
number = {4},
pages = {111-115},
issn = {2349-6002},
url = {https://ijirt.org/article?manuscript=208035},
abstract = {Multiplication is regarded as a fundamental arithmetic operation by which the speed, area, and energy efficiency of digital systems are directly affected. In this paper, a comparative implementation and performance analysis of five multiplier architectures that are Array, Booth, Dadda, Vedic, and Wallace is presented using VHDL and FPGA synthesis. These architectures are evaluated for operand widths of 2, 4, 8, and 16 bits across four Xilinx FPGA families: Artix-7, Kintex-7, Spartan-3E, and Virtex-7. Propagation delay, LUT utilization, and logical depth are devoted as the principal performing indicators, allowing both timing and hardware-resource requirements to be compared. It is shown by the results that the most beneficial timing performance for medium- and large-sized operands is provided by Dadda multiplication, whereas competitive resource utilization, particularly in smaller designs, is achieved by Vedic multiplication. Elevated delay and greater resource requirements are constantly exhibited by the Spartan-3E device than by the newer 7-series devices. It is therefore demonstrated that multiplier selection should be determined by the requirements of the intended application, with Dadda architectures being favored for timing-critical implementations and Vedic architectures being considered attractive for area-constrained designs.},
keywords = {FPGA; Vedic multiplier; Dadda multiplier; Booth multiplier; Wallace multiplier; Array multiplier; propagation delay; LUT utilization; digital arithmetic},
month = {September},
}
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