Design of Low Power NAND-NOR Content Addressable Memory (CAM) Using SRAM
Author(s):
VENKATESH Vaidhyam Kannan, Rekha CS, Deepthi Vijay Kundar, Akshatha Arjun Babu Naidu
ISSN:
2349-6002
Cite This Article:
Design of Low Power NAND-NOR Content Addressable Memory (CAM) Using SRAMInternational Journal of Innovative Research in Technology(www.ijirt.org) ,ISSN: 2349-6002 ,Volume 6 ,Issue 3 ,Page(s):185-190 ,August 2019 ,Available :IJIRT148592_PAPER.pdf
Keywords:
Bit line, Content addressable memory (CAM), match line, NAND CAM, NAND-NOR architecture, NOR CAM, search line, single bit line SRAM, Static random access memory (SRAM)
Abstract
Content addressable memory (CAM) is a type of computer memory used in high speed searching applications. A content addressable memory (CAM) compares input data to the existing stored data in memory and returns the address of the matching data. A CAM usually contains SRAM cell with a comparison circuitry that enables search operations to complete in single clock cycle. In case of advanced applications we need large sized CAM which leads in more power consumption. In order to reduce the power consumed by the CAM cell, the memory circuits used are 6T SRAM and single bit line SRAM as the core storage element. Single bit line SRAM consumes 46.3 percent of power lesser than 6T SRAM. This paper discusses the implementation of two different architectures of CAM cells namely NAND and NOR type. Power consumption of both architectures are analysed and an efficient NAND-NOR type CAM cell is implemented to overcome its limitations.
Article Details
Unique Paper ID: 148592

Publication Volume & Issue: Volume 6, Issue 3

Page(s): 185 - 190
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