The design of low power high performance 2-D Discrete Wavelet Transform (DWT) unit is presented in this paper. A low power multiplier with hybrid encoding scheme is proposed to reduce the power consumption compared with other common multipliers. Multiplication is the main arithmetic operation used in the lifting scheme of the DWT and the proposed method reduces the total power requirements. The lifting step and multiplier are designed and synthesized using XILINX SPARTRN 3E Field Programmable Gate Array (FPGA). The power consumption of the DWT with hybrid encoded Booth multiplier is compared with existing array and Booth multiplier. The simulation results show the total power dissipation of the DWT with hybrid multiplier saves 90% and 76% power compared with array and Booth multiplier.