In recent years, due to the rapid growth of high performance digital systems, speed and power consumption become very vital in multiplier design. In this paper, a Vedic multiplier has been designed using the combination of Urdhva Triyakbyam Sutra and Carry Save Adder. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which minimize the number of partial products compared to the conventional multiplication algorithm. The multiplier is simulated using Microwind Tools with General Process Design Kit (GPDK) of 45, 65, 90 nm CMOS technologies using several voltage supplies to find the most optimum value for the voltage supply to be used. The result shows that with the usage of 1 V voltage supply, the new design of multiplier using a combination of CSA and Vedic mathematics can produce the lowest power consumption and least delay time. Vedic multiplier is able to yield a full output voltage swing with a power consumption is 0.215 mW in 45nm , 0.235 mW in 65nm and 1.410 mW in 90 nm. delay of 0.27 ns in 45nm, 0.54 ns and 0.72 ns. compact area of 898.6 µm2 in 45nm, 2752.1 in 65nm, 4549.4 µm2 in 90 nm.