POWER REDUCTION IN SRAM CELLS USING GATED VDD METHODOLOGY
Author(s):
T.Mani, R.Priya, K.Parveen Banu, P.Reena
Keywords:
Abstract
The most significant component of portable battery-operated digital devices is memories. Since standard SRAM cells consume a lot of capacity, lowering memory power dissipation helps the device work better. In this new age of fast mobile computing, traditional SRAM cell designs are power hungry and underperforming. A static RAM with a low power consumption. The Gated VDD technique is used to investigate cell architecture. The SRAM cell's power consumption has been reduced using gated VDD and MTCMOS architecture techniques. In terms of power consumption and write delay, the results show that the MTCMOS-based SRAM cell is the best performer. Simulations are run on the Cadence Virtuoso tool, which uses 180nm technology.
Article Details
Unique Paper ID: 151425

Publication Volume & Issue: Volume 7, Issue 12

Page(s): 670 - 673
Article Preview & Download


Share This Article

Conference Alert

ICM - STEP

International conference on Management, Science, Technology, Engineering, Pharmact and Humanities.

Latest Publication

Go To Issue



Call For Paper

Volume 7 Issue 9

Last Date 25 February 2020

About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Google Verified Reviews

Contact Details

Telephone:6351679790
Email: editor@ijirt.org
Website: ijirt.org

Policies