Design and Implementation of PRPG with Low Transition Test CompressionTechnique
Hajari Manisha, Devendher kanoor, Gopi Kondra
Built-In Self-Test (BIST), Circuit Under Test (CUT),PRPG, test data volume compression.
This project describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)- based pseudorandom test pattern generators. It comprised of finite state machine LFSR driving a phase shifterand it allows the device to produce binary sequence with preselected toggling activity. Generator is automatically controlled providingeasy and precise tuning. Furthermore, this paper introduces a test compression method to avoid repeated pattern generation for testingthe same device. The main highlight of this paper is to reduce the test data volume and test data memory.The proposed LPPRPG is designed using Verilog HDL.
Article Details
Unique Paper ID: 144170

Publication Volume & Issue: Volume 3, Issue 7

Page(s): 201 - 205
Article Preview & Download

Share This Article

Join our RMS

Conference Alert

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

Call For Paper

Volume 11 Issue 1

Last Date for paper submitting for Latest Issue is 25 June 2024

About Us enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on

Social Media

Google Verified Reviews