Novel Approach for implementation BISR (Built In Self Repair) With Redundancies in a System On-Chip For SRAMS
Author(s):
B. NAGAMANI, D. MUTHILINGAM
Keywords:
Redundancy Analysis, SoC, SRAM, MBISR.
Abstract
Therefore, we implemented an MBISR generator called BRAINS+, which automatically generates register transfer level MBISR circuits for SoC designers. The MBISR circuit is based on a redundancy analysis (RA) algorithm that enhances the essential spare pivoting algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal operation, e.g., with a typical 0.13μm complementary metal- oxide-semiconductor technology, it can run at 333 MHz for a 512 Kb memory with four spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.
Article Details
Unique Paper ID: 144657

Publication Volume & Issue: Volume 4, Issue 1

Page(s): 304 - 307
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