VLSI Implementation of High Performance Montgomery Modular Multiplication for Crypto graphical Application
Baana Lakshmi Narayanamma, B.Aruna
This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. Full-adder or two serial half-adders, is proposed to reduce the extra clock cycles for operand pre computation and format conversion by half. In addition, a mechanism that can detect and skip the unnecessary carry-save addition operations in the one-level CCSA architecture while maintaining the short critical path delay is developed. As a result, the extra clock cycles for operand pre computation and format conversion can be hidden and high throughput can be obtained. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance and significant area–time product Improvement when compared with previous design.
Article Details
Unique Paper ID: 144799

Publication Volume & Issue: Volume 4, Issue 4

Page(s): 56 - 64
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