Optimized Bira Technique for VLSI Processors

Kinda Shiva; Lali RajKumar

Optimized Bira Technique for VLSI Processors

Authors: Kinda Shiva, Lali RajKumar

Unique Paper ID: 145004
Volume: 4
Issue: 6
PageNo: 373-376

Keywords: BIRA Pseudo Random Number VLSI

Abstract:
In this paper, Built in self repair scheme(BISR) uses the built in self test(BIST) and Built in repair analysis(BIRA). BIST is used test and detect faulty memories. It send the fault information to BIRA. BIRA is used to find the repair solutions to the faulty memories. Among hiding counter measures, essentially distinguish strategies: one based on the randomisation of the execution of cryptographic algorithms one or more Pseudo Random Number Generators (PRNGs) are also included to generate the masks, which should be updated at each step of the datapath for a more efficient masking scheme. Prng used to generate key values to overcome the limitations of manual insertion values.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 6
PageNo: 373-376

Optimized Bira Technique for VLSI Processors

Available:https://ijirt.org/Article?manuscript=145004

Impact Factor
8.01 (Year 2024)

UGC Approved
Journal no 47859

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