Parallel CMOS Implementation of NOR Logic in both Pull-Up and Pull-Down Networks
Author(s):
Noor Ul Abedin
Keywords:
CMOS, NOR, Pull-up, Pull-down, Parallel and DSCH software
Abstract
Aware to that the implementation of CMOS logic based on NAND and NOR logic principles of pull-up and pull-down combination of transistors, this work shows how by using both the combinations of pull-up and pull-down transistors in parallel too we can realize a NOR logic. This is illustrated with the help of using DSCH software.
Article Details
Unique Paper ID: 145330
Publication Volume & Issue: Volume 4, Issue 9
Page(s): 187 - 190
Article Preview & Download
Share This Article
Conference Alert
NCSST-2023
AICTE Sponsored National Conference on Smart Systems and Technologies
Last Date: 25th November 2023
SWEC- Management
LATEST INNOVATION’S AND FUTURE TRENDS IN MANAGEMENT