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Parallel CMOS Implementation of NOR Logic in both Pull-Up and Pull-Down Networks

  • Unique Paper ID: 145330
  • Volume: 4
  • Issue: 9
  • PageNo: 187-190
  • Abstract:
  • Aware to that the implementation of CMOS logic based on NAND and NOR logic principles of pull-up and pull-down combination of transistors, this work shows how by using both the combinations of pull-up and pull-down transistors in parallel too we can realize a NOR logic. This is illustrated with the help of using DSCH software.
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  • ISSN: 2349-6002
  • Volume: 4
  • Issue: 9
  • PageNo: 187-190

Parallel CMOS Implementation of NOR Logic in both Pull-Up and Pull-Down Networks

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Journal no 47859

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