A Power Efficient Low input 12nm FinFET Level Shifter for near threshold circuits
Radhika, Dr. Jayadeva T S
12nm FinFET's, level shifter, low power, near threshold circuits.
Power has transformed into the basic arrangement plan for chip designers today. While moore's law sustain to give extra transistors, power related requirements have begun to block those devices from being used. Nowadays, low power outlines, especially multi-voltage designs transforms into a notable and capable way to deal with decrease in both dynamic power and static power utilization. A key parameter in outlining of powerful multi supply circuits is restricting the cost of the level change between different voltage spaces while keeping up the general strength of the design. To such a reason, level shifter (LS) circuits can be utilized. So as to accomplish lessening in power utilization, a proposed level shifter topology has been used as a part of this paper which utilizes a low dispute amongst PMOS and NMOS transistor because of which dynamic vitality utilization is decreased, speed is likewise expanded because of the utilization of criticism circle and furthermore because of the close limit figuring its vitality productivity is more. As 12nm innovation node conveys better thickness and an execution help over Global Foundries' present age 14nm FinFET, which fulfills the handling needs of the most requesting computer intensive applications from artificial intelligence and virtual reality to top of the line advanced cells and systems administration foundation, the proposed level shifter has been downsized to 12nm innovation node which is equipped for changing over close limit voltage level to above edge voltage signal(i.e. from 250mV to 500mV) with 284.1229nW of power dissipation.
Article Details
Unique Paper ID: 146502

Publication Volume & Issue: Volume 5, Issue 1

Page(s): 113 - 118
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