Design of High Speed Clocked Comparators: A Survey

VISHAL GANPAT DALVI; deepak sharma

Design of High Speed Clocked Comparators: A Survey

Authors: VISHAL GANPAT DALVI , deepak sharma

Unique Paper ID: 146635
Volume: 5
Issue: 1
PageNo: 420-423

Keywords: High speed ADCs Double-tail comparator Dynamic clocked comparator

Abstract:
Comparators are basic building elements for designing modern analog and mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents a design for an on chip high-speed dynamic latched comparator for high frequency signal digitization. The dynamic latched comparator consists of two cross coupled inverters comprising a total of 9 MOS transistors. The measured and simulation results show that the dynamic latched comparator design has higher speed, low power dissipation and occupying less active area compared to double tail latched and preamplifier based clocked comparators. A new fully dynamic latched comparator which shows lower offset voltage and higher load drivability than the conventional dynamic latched comparators has been designed. With two additional inverters inserted between the input-stage and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability. Hence the paper lays down the foundation for a high speed comparator.

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Cite This Article

ISSN: 2349-6002
Volume: 5
Issue: 1
PageNo: 420-423

Design of High Speed Clocked Comparators: A Survey

Available:https://ijirt.org/Article?manuscript=146635

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