Implementation of 16 bit RISC Processor by FSM

Manoj Barfa; Deepak Sharma

Implementation of 16 bit RISC Processor by FSM

Authors: Manoj Barfa, Deepak Sharma

Unique Paper ID: 146367
Volume: 4
Issue: 12
PageNo: 409-414

Keywords: Arithmetic logical unit (ALU); control unit (CU);comparator; shifter; rotation; instruction se; VERILOGHDL; Xilinx.

Abstract:
The central unit of all smart devices are Processors, whether they be electronic devices or otherwise. Their smartness comes as a direct result of the decisions and controls that processor makes. The existing commercial microprocessors are provided as black box units; with which users are unable to monitor internal signals and operation process, neither can they modify the original structure. In order to solve this problem 16-bit fully functional single cycle processor is designed in terms of its architecture and its functional capabilities. The procedure of design and verification for a 16-bit processor is introduced in this paper. The key architecture elements are being described, as well as the hardware block diagram and internal structure. The summary of instruction set is presented. This processor is modify as a VERILOG Hardware Description Language (VERILOGHDL) and gives access to every internal signal. In order to consume fewer resources, the design of arithmetic logical unit (ALU) is optimized. The RTL views and verified simulation results of processor are shown in this paper. The synthesis report of the design is also described. The design architecture is written in VERILOG Hardware Description Language (VERILOGHDL) code using Xilinx ISE tool for synthesis and simulation.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 12
PageNo: 409-414

Implementation of 16 bit RISC Processor by FSM

Available:https://ijirt.org/Article?manuscript=146367

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