AREA EFFICIENT RIPPLE CARRY ADDER USING 22nm STRAINED SILICON CMOS TECHNOLOGY

J. Swathi; K. Muthusamy; Athira Rajagopal

AREA EFFICIENT RIPPLE CARRY ADDER USING 22nm STRAINED SILICON CMOS TECHNOLOGY

Authors: J. Swathi, K. Muthusamy, Athira Rajagopal

Unique Paper ID: 154181
Volume: 8
Issue: 10
PageNo: 271-275

Keywords: Ripple Carry Adder AOI Gates OAI Gates Binary tree adder

Abstract:
In this research proposal, the existing ripple carry adder (RCA) is analysed to find the possibilities for area minimization. Based on the analysis, the full adder is further modified with OAI circuit and AOI circuit and the corresponding design of RCA are proposed for the BTA. The RCA is designed for m bits (m=8,16,32 bits) has reduced in transistors count than the existing RCA. Using this RCA design, the multi-operand adder (n=8) BTA structure is proposed. The RCA and Binary tree structure is synthesised at 22nm CMOS technology. Result reveals that the proposed RCA and BTA-MOA provides the efficient results in area minimization compared to previous structure, suitable for multipliers and other applications. Therefore, this modified ripple carry adder based binary tree adder can be a better choice to develop the efficient digital systems for signal and image processing applications.

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ISSN: 2349-6002
Volume: 8
Issue: 10
PageNo: 271-275

AREA EFFICIENT RIPPLE CARRY ADDER USING 22nm STRAINED SILICON CMOS TECHNOLOGY

Available:https://ijirt.org/Article?manuscript=154181

Impact Factor
8.01 (Year 2024)

UGC Approved
Journal no 47859

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