AREA EFFICIENT RIPPLE CARRY ADDER USING 22nm STRAINED SILICON CMOS TECHNOLOGY
Author(s):
J. Swathi, K. Muthusamy, Athira Rajagopal
Keywords:
Ripple Carry Adder, AOI Gates, OAI Gates, Binary tree adder
Abstract
In this research proposal, the existing ripple carry adder (RCA) is analysed to find the possibilities for area minimization. Based on the analysis, the full adder is further modified with OAI circuit and AOI circuit and the corresponding design of RCA are proposed for the BTA. The RCA is designed for m bits (m=8,16,32 bits) has reduced in transistors count than the existing RCA. Using this RCA design, the multi-operand adder (n=8) BTA structure is proposed. The RCA and Binary tree structure is synthesised at 22nm CMOS technology. Result reveals that the proposed RCA and BTA-MOA provides the efficient results in area minimization compared to previous structure, suitable for multipliers and other applications. Therefore, this modified ripple carry adder based binary tree adder can be a better choice to develop the efficient digital systems for signal and image processing applications.
Article Details
Unique Paper ID: 154181

Publication Volume & Issue: Volume 8, Issue 10

Page(s): 271 - 275
Article Preview & Download


Share This Article

Conference Alert

NCSST-2021

AICTE Sponsored National Conference on Smart Systems and Technologies

Last Date: 25th November 2021

SWEC- Management

LATEST INNOVATION’S AND FUTURE TRENDS IN MANAGEMENT

Last Date: 7th November 2021

Go To Issue



Call For Paper

Volume 10 Issue 1

Last Date for paper submitting for March Issue is 25 June 2023

About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Google Verified Reviews

Contact Details

Telephone:6351679790
Email: editor@ijirt.org
Website: ijirt.org

Policies