design of approximate multiplier using 5:2 compressor
Author(s):
B.Sree Mangamma, M.MadhuBabu
Keywords:
Approximate 5:2 compressors, Approximate Computing, approximate multipliers, error robust applications.
Abstract
High-speed multimedia applications have ushered in a new era of approximation-based errortolerant circuits. These programmes provide great performance at the expense of precision. In addition, such approaches minimize system complexity, latency, and power consumption. When compared to conventional method, this is a significant improvement. This study looks at and suggests the design and analysis of two approximation compressors that are smaller, have less delay, and use less power while maintaining the same accuracy. The proposd designs have been carefully evaluated and projected on several scales, including area and time. When compared to a compressor-based approximation multiplier with a ratio of 4: 2, the suggested approximate 5: 2 compressor reduced area and delay16*16 Dadda multipliers are used with the given compressors. These multipliers are on par with state-of-the-art approximation multipliers in terms of accuracy. The research is being expanded to evaluate use of the suggested architecture in error-tolerant applications such as image smoothing and image multiplication.
Article Details
Unique Paper ID: 154363

Publication Volume & Issue: Volume 8, Issue 11

Page(s): 447 - 452
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