Design of High Efficient Video Encoder H.265

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ISSN: 2349-6002 ESTD Year: 2014

UGC approved journal no 47859

Design of High Efficient Video Encoder H.265
Author(s):
Akash.H.Deepak , Vijayaprakash A.M
Keywords:
H.265 Encoder, Verilog, FPGA, Xilinx,Genus
Abstract
In this project, we have designed an efficient Motion Estimation (ME) processor or engine for High Efficiency Video Coding (HEVC) systems is presented, along with its algorithm and VLSI architecture.The Exhaustive Search Algorithm that is implemented in this project, in particular, dramatically reduces the number of search possibilities while customizing the search space to the characteristics of the video.According to the experimental findings, this algorithm reduces computational complexity by 54% compared to traditional methods with just a slight performance hit of 2.01%. Additionally, this article presents the suggested ME engine's VLSI design and circuit implementation. Illustrated are the system level and gate level optimizations for increasing efficiency and lowering complexity.
Article Details
Unique Paper ID: 156811 Publication Volume & Issue: Volume 9, Issue 5 Page(s): 65 - 72
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