Design of Asynchronous SAR ADC of 10-bit With EA-based bandgap reference voltage generator using bootstrap switch & Two stage dynamic comparator
Author(s):
SURENDRA LOYA, Kiran Kumar K, TEJA SEETHARAMA K, Karthik M, Venkata Harish V
Keywords:
Asynchronous SAR logic and comparator clock generator; bandgap reference voltage generator; two-stage dynamic comparator; low power consumption.
Abstract
The proposed prototype of a 10-bit asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an EA-based bandgap reference voltage generator is designed to optimize power consumption, static, and dynamic performance. Several techniques are proposed to achieve these objectives. One of the proposed techniques is the dual-path bootstrap switch, which aims to increase the linearity of sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique is also implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. This helps to reduce power consumption while maintaining dynamic performance.The proposed architecture of the two-stage dynamic latch comparator is another technique to achieve high speed and low power consumption. This helps to reduce the time required for bit conversion, which is important for practical applications. To achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock. All conversions are carried out in a single clock cycle, making the ADC more efficient. Finally, the proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC, which is essential for accurate conversion. The EA-based bandgap reference voltage generator helps to improve the static performance of the ADC.
Article Details
Unique Paper ID: 159072

Publication Volume & Issue: Volume 9, Issue 11

Page(s): 275 - 287
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