IMPLEMENTATION OF POLAR CODES USING VERILOG HDL FOR 5G APPLICATIONS

IMPLEMENTATION OF POLAR CODES USING VERILOG HDL FOR 5G APPLICATIONS
Author(s):
Parasa vinusha, Dr.E Sarva ramesarudu
Keywords:
Polar codes, MAP, VLSI
Abstract
This paper proposes Very Large Scale Integration (VLSI) architecture for the implementation of Polar decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximum-a- Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this project uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder side. Beyond-5G systems are expected to operate at Terabit/s data rates. Today’s most advanced polar code implementations currently deliver only around 5Gbps. Therefore, Turbo codes and LDPC codes that played key enablers in 3G and 4G systems are already unproven for many new 5G applications. Polar code is believed as prominent breakthrough in 5G. It guarantees apical performance for 5G scenarios and hence it is considered as a promising candidate for the 5G New Radio. This work accentuates on the suitability of polar codes for the 5G scenarios.
Article Details
Unique Paper ID: 160836 Publication Volume & Issue: Volume 10, Issue 1 Page(s): 1331 - 1335
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