ULTRA LOW POWER VOLTAGE DEVIATE-DOMINO LOGIC CIRCUITS WITH LOW NOISE TOLERANCE SYSTEM

ULTRA LOW POWER VOLTAGE DEVIATE-DOMINO LOGIC CIRCUITS WITH LOW NOISE TOLERANCE SYSTEM
Author(s):
E.Lenin, Dr.K.Somu, V.Suresh
Keywords:

Abstract
A new noise-tolerant dynamic CMOS circuit approach is suggested with improved domino CMOS logic behaviour. Domino logic circuits are frequently chosen in high-performance designs due to their advantages of high speed and low area overhead. But in integrated circuits, the power used by clocking gradually becomes a determining factor. For this reason, the main goal of this research is to examine the performance of a voltage deviate-domino circuit using the Prescient Innovation Model (PIM) control method to compare the effectiveness of various domino techniques in terms of delay, power, and their outputs, such as the figure of merit on the spice model when using an EDA tool on a 0.18-micron CMOS process technology Utilising spice model EDA, the proposed PIM voltage deviate domino logic is created. The performance of proposed voltage deviate domino circuit is validated through simulation. The simulation results demonstrate the reduction improvement in the noise immunity, power consumption, delay and similar noise of results has to be demonstrated power reduction and speed change in voltage variation-Domino Circuit Registry file associated with the regular Registry file.
Article Details
Unique Paper ID: 161007 Publication Volume & Issue: Volume 10, Issue 2 Page(s): 305 - 309
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