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Design and implementation of reconfigurable placement technique in soc.

  • Unique Paper ID: 161217
  • Volume: 10
  • Issue: 2
  • PageNo: 954-960
  • Abstract:
  • One of the most crucial processes for design closure is placement for very-large-scale integrated (VLSI) circuits. By equating the analytical placement problem to the process of training a neural network, we provide a revolutionary GPU-accelerated placement framework called DREAMPlace. DREAMPlace, which is built on top of the widely used deep learning framework PyTorch, can outperform the state-of-the-art multithreaded placer RePlAce in terms of global placement speed without sacrificing quality by about 40 percent. We think that our effort will pave the way for tackling old EDA issues using modern hardware and software for AI.
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  • ISSN: 2349-6002
  • Volume: 10
  • Issue: 2
  • PageNo: 954-960

Design and implementation of reconfigurable placement technique in soc.

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