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@article{164897,
        author = {A Aakash and Aparna R and Abey Biju Abraham and Malathi S R},
        title = {DESIGN OF 5 stage PIPELINED RISC-V PROCESSOR},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {10},
        number = {12},
        pages = {2779-2782},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=164897},
        abstract = {This paper presents a modified design of RISC-V RV32I 32-bit microprocessor. The RISC-V processor consists of a flexible 5 stage pipelined processor with certain techniques for hazard management. The processor consists of 6 blocks- fetch block, decode block, control logic block, memory block, register block and the ALU block. The processor is then pipelined into 5 stages – the fetch stage, the decode stage, the execute stage, the memory stage and the write backstage. After pipelining, the pipeline hazards such as data hazards and control hazards are managed by using data forwarding from previous stages of the pipeline and by introducing delay slots for control transfer instructions. After that, the schematic for the processor is obtained by feeding the Verilog code in cadence software. Also, there is a future scope of implementing new instructions that can combine the functions of two separate instructions into one single instruction, which are considered extensions to the existing ISA of RV32I.},
        keywords = {RV32I, Flexibility, 5 stage pipelined, hazard management, 5 clock cycles.},
        month = {},
        }