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Study and Analysis of Universal Gates using different logic styles at CMOS Logic Style at 45nm Technology

  • Unique Paper ID: 166142
  • Volume: 11
  • Issue: 2
  • PageNo: 299-306
  • Abstract:
  • Research into the design and performance analysis of NAND and NOR gates using CMOS logic at 45nm technology is a captivating subject in the field of VLSI design. NAND and NOR gates because they are universal gates and they can form all basic gates (AND, OR, NOT, XOR, XNOR) and any logical Boolean expression can be implemented using only NAND gates or only NOR gates. The investigation involves the creation of two-input NAND and NOR gates using a variety of logic styles and the subsequent analysis of their performance in terms of average power consumption, average propagation delay, power-delay product, and transistor count. The technology employed is 45nm. The study offers an in-depth understanding of the workings of NAND and NOR gates. Additionally, the delay, rise time, and fall time are computed. The research findings indicate that the NAND gate has several advantages over the NOR gate, including lower static and dynamic power dissipation, smaller area requirement, reduced rise and fall times, and significantly lower delay. This knowledge equips engineers with the ability to develop increasingly sophisticated and efficient digital systems. By understanding these configurations, the abstract lays the groundwork for further exploration of complex digital circuits built upon these fundamental NAND and NOR gates. The construction and testing of NAND and NOR gates have been performed using Tanner EDA v15. An in-depth examination of delay and power for various logic styles of the NAND and NOR gate has been conducted. Additionally, a comprehensive Process, Voltage, Temperature (PVT) analysis has been executed for the circuits.
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  • ISSN: 2349-6002
  • Volume: 11
  • Issue: 2
  • PageNo: 299-306

Study and Analysis of Universal Gates using different logic styles at CMOS Logic Style at 45nm Technology

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