Author Login IJIRT Partner Network (IPN) Login

Optimized MAC Unit using Binary Carry Select Adder and Counter-Based Modular Wallace Tree Multiplier

  • Unique Paper ID: 167518
  • Volume: 11
  • Issue: 3
  • PageNo: 1568-1572
  • Abstract:
  • The multiply accumulate unit are crucial components in high-performance computing devices, particularly embedded systems. These units consist of a accumulator, multiplier, and adder, and perform operations by reading input from memory cells, multiplying it within MAC multiplier block, adding the result, and storing it back in memory—all within one clock cycle.To increase the efficiency of these units, a novel design MFA-MAC is proposed that improves speed while consuming less power. This design employs three separate blocks are combined with the high-speed binary carry select adders inside the MAC units: final carry generators (FCG), final sum generators (FSG), and half sum with carry generators (HSCG). A CMWTM was used for the multiplier design, incorporating power-saving techniques. Additionally, the application of MFA significantly reduces power usage by simply turning off at certain areas of the circuit when they're not in use, thus achieving a more power-efficient and faster MAC unit suitable for embedded systems.
Download article email to a friend

Cite This Article

  • ISSN: 2349-6002
  • Volume: 11
  • Issue: 3
  • PageNo: 1568-1572

Optimized MAC Unit using Binary Carry Select Adder and Counter-Based Modular Wallace Tree Multiplier

Related Articles

Impact Factor
8.01 (Year 2024)
UGC Approved
Journal no 47859

Join Our IPN

IJIRT Partner Network

Submit your research paper and those of your network (friends, colleagues, or peers) through your IPN account, and receive 800 INR for each paper that gets published.

Join Now

Latest Publication

Archive

View More

Recent Conferences

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024 Last Date: 15th March 2024

Submit inquiry