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@article{167518,
        author = {NAVANEETHA H D and Dr. Vidyasaraswathi H N},
        title = {Optimized MAC Unit using Binary Carry Select  Adder and Counter-Based Modular Wallace  Tree Multiplier},
        journal = {International Journal of Innovative Research in Technology},
        year = {2024},
        volume = {11},
        number = {3},
        pages = {1568-1572},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=167518},
        abstract = {The multiply accumulate unit are crucial components in high-performance computing devices, particularly embedded systems. These units consist of a accumulator, multiplier, and adder, and perform operations by reading input from memory cells, multiplying it within MAC multiplier block, adding the result, and storing it back in memory—all within one clock cycle.To increase the efficiency of these units, a novel design MFA-MAC is proposed that improves speed while consuming less power. This design employs three separate blocks are combined with the high-speed binary carry select adders inside the MAC units: final carry generators (FCG), final sum generators (FSG), and half sum with carry generators (HSCG). A CMWTM was used for the multiplier design, incorporating power-saving techniques. Additionally, the application of MFA significantly reduces power usage by simply turning off at certain areas of the circuit when they're not in use, thus achieving a more power-efficient and faster MAC unit suitable for embedded systems.},
        keywords = {Multiply-accumulate unit ,counter based modular Wallace tree multiplier, partial product reduction.},
        month = {August},
        }