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Power-Efficient SPI-Based BIST Design Using Clock Gating Method

  • Unique Paper ID: 167576
  • Volume: 11
  • Issue: 3
  • PageNo: 1756-1761
  • Abstract:
  • In modern electronic systems, power efficiency is a critical design consideration, particularly in embedded systems where power resources are limited. Built-in Self-Test (BIST) methodologies are widely employed to ensure system reliability and facilitate fault detection and diagnosis. However, BIST implementations often introduce additional power utilization, which will be detrimental in power-sensitive applications. This project explores the optimization of power efficiency in Serial Peripheral Interface (SPI)-based BIST systems through the implementation of clock gating techniques. Clock gating is a dynamic energy optimization approach that minimizes power utilization by disabling the clock signal to idle modules, thereby minimizing switching activity. By integrating clock gating into the SPI-based BIST architecture, we aim to achieve significant reductions in power usage without compromising test coverage or performance. The proposed methodology involves designing a clock gating controller that dynamically monitors the activity of the SPI modules and selectively gates the clock signals. Our results indicate that the power utilization of the SPI-based clock-gated BIST system is reduced by up to 10.12% compared to a non-clock-gated SPI BIST system. Additionally, the area of the SPI-based clock- gated BIST is reduced by up to 8.42% compared to the non- clock-gated SPI BIST system.
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  • ISSN: 2349-6002
  • Volume: 11
  • Issue: 3
  • PageNo: 1756-1761

Power-Efficient SPI-Based BIST Design Using Clock Gating Method

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