Comparative Analysis of 7T,10T And 12T SRAM Scheme For Upcoming VLSI Design

Pratik Kumar Dubey; Unnati Gaur; Pari Sharma

Comparative Analysis of 7T,10T And 12T SRAM Scheme For Upcoming VLSI Design

Authors: Pratik Kumar Dubey, Unnati Gaur, Pari Sharma

Unique Paper ID: 178002
Volume: 11
Issue: 12
PageNo: 3407-3410

Keywords: Write Delay Read Delay Static Noise Margin (SNM) Power Consumption SRAM CMOS Technology.

Abstract:
This study explores and analyzes CMOS SRAM cells utilizing advanced technology nodes, with a focus on three distinct architectures: the 7-transistor (7T), 10-transistor (10T), and 12-transistor (12T) SRAM cells. The primary objective is to assess their performance through simulations conducted in Cadence Virtuoso, evaluating critical metrics such as power consumption, Static Noise Margin (SNM), read delay, and write delay. The design methodology involves schematic design and simulation of each SRAM cell type under various operating conditions to investigate their functionality and performance characteristics. Simulation results reveal trade-offs among the architectures, with the 7T cell offering a balance of simplicity and efficiency, the 10T cell providing enhanced stability, and the 12T cell excelling in low-power and high-reliability applications. These findings underscore the potential for selecting an appropriate SRAM architecture based on specific application requirements, optimizing for performance, area efficiency, and robustness in emerging technologies.

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ISSN: 2349-6002
Volume: 11
Issue: 12
PageNo: 3407-3410

Comparative Analysis of 7T,10T And 12T SRAM Scheme For Upcoming VLSI Design

Available:https://ijirt.org/Article?manuscript=178002

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