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@article{143290,
        author = {Ritika Tiwari and Vijay Sharma and Megha Soni},
        title = {Design of ring VCO based PLL using 0.25 µm CMOS technology},
        journal = {International Journal of Innovative Research in Technology},
        year = {2016},
        volume = {2},
        number = {9},
        pages = {52-56},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=143290},
        abstract = {A low power ring VCO based PLL using injection locking is realized by adopting 0.25µm CMOS technology at 2.5V. We have achieved a shift in the bias level by using pMOS active resistive load. The PLL output frequency is 104.4 MHz, at 5 MHz reference frequency by using injection locking based VCO and active resistive load managed to achieve low power dissipation of 4.98mW at 2.5 V.},
        keywords = {Phase Locked Loop, Injection Locking, Ring VCO, Shift Bias Level.},
        month = {February},
        }