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@article{144624,
        author = {Spoorthi B R and Nayana M and Siva Yellampalli},
        title = {Design and Implementation of Efficient Reconfigurable Router for Network on Chip (NoC) Using FPGA},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {1},
        pages = {257-261},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=144624},
        abstract = {Nowadays, most SOC’s use NoC as interconnect architecture instead of bus based communication architecture, due to its layered data transfer and reduced latency. But, the use of router for each switch increases the power dissipation of the entire architecture. This problem can be solved by using reconfigurable router. This paper presents the reconfigurable router which reduces the overall power dissipation without compromising the performance. The proposed architecture is implemented and power is approximately reduced by 25 % when compared to conventional architecture.},
        keywords = {NoC, Reconfigurable Router, FIFO Buffer, Crossbar Switch, FIFO Control logic, Arbiter, Low Power.},
        month = {},
        }