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@article{145081,
        author = {G.CHANDANA  and P.RAJANI},
        title = {FAST PARALLEL PREFIX  MODULO 2n+1 ADDER},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {7},
        pages = {276-277},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=145081},
        abstract = {Two architectures for modulo 2n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n+1 addition. This sparse approach is enabled by the introduction of the inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high Operation speed. The second architecture unifies the design of modulo 2n-1 adders. It is shown that modulo 2n-1 adders can be easily derived by straightforward modifications of modulo 2n-1 adders with minor hardware overhead.
},
        keywords = {Parallel-Prefix, Potency},
        month = {},
        }