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@article{145254,
        author = {Roopa Rao and Amaresha S.K},
        title = {Design and Implementation of Pipelined AES Algorithm on FPGA},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {8},
        pages = {149-155},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=145254},
        abstract = {The paper presents high speed architecture for the hardware implementation of the Advanced Encryption Standard (AES) Algorithm. The proposed design employs a Galois Field, GF(28), SubBytes (S-Box) transformation based on Rijndael algorithm in the Field Programmable Gate Arrays (FPGAs). The implementation of S-Box carried out by two stages pipelining for the small area occupancy and high throughput. In addition key expansion architecture suitable for the pipelined AES also presented. The design is implemented and synthesized using Xilinx ISE v13.4 and Xilinx Spartan-3E XC3S2500E-4 as a target device. The timing results from the Place and Route report indicate that area occupied by this architecture is 67% of the slices.},
        keywords = {AES, Composite Field, FPGA, Galois Field, Key expansion,pipelined S-Box, Rijndael.},
        month = {},
        }