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@article{146303,
        author = {M.M. Prasada Reddy},
        title = {DESIGN AND SIMULATION OF 2-BIT FULL SUB TRACTOR AT 32 nm CMOS TECHNOLOGIES},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {12},
        pages = {131-133},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=146303},
        abstract = {Low power and efficient area are frequently required in very large scale integration design. The Complementary Metal Oxide Semiconductor (CMOS) are used in various electronic fields viz manufacturing of digital integrated circuits, microcontrollers and microprocessors. In this paper, the proposed CMOS 2- bit full Subtractor is simulated and analyzed using Microwind 3.1at 32nm CMOS technologies. The full Subtractor is sowing good performance in terms of power dissipation and area. },
        keywords = {CMOS, VLSI, Full Subtractor, Power consumption, CMOS technology},
        month = {},
        }