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@article{147166,
        author = {S.V. PAVAN KALYAN and K. NAGA SANKAR REDDY},
        title = {AN EFFICIENT MULTIPLIER BASED ON SHIFT AND ADD ARCHITECTURE},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {5},
        number = {5},
        pages = {96-101},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=147166},
        abstract = {In this paper, a low-power shape known as skip zero, feed A immediately (BZ-FAD) for shift-and-add multipliers is planned. The architecture appreciably lowers the switching pastime of traditional multipliers. The modifications to the multiplier that increases through contain the elimination of the transferring the sign in, direct feeding off to the adder, avoiding the adder every time feasible, by means of a ring oppose in place of a binary counter and taking away of the incomplete product shift. The architecture creates utilize of a low-energy ring oppose planned on this paintings.  Simulation outcomes for 32-bit radix-2 multipliers display that the BZ-FAD structure lowers the entire switching hobby up to seventy six% and electricity intake to the extent that 30% while as evaluated to the predictable structure. The proposed multiplier may low-power programs that rate which were not primary layout parameter.},
        keywords = {},
        month = {},
        }