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@article{148543,
        author = {Peddi venkatesh and S.Saidarao},
        title = {LOW POWER AND AREA EFFICIENT SYSTEM WITH ONE-CYCLE CORRECTION OF TIMING ERRORS IN PIPELINES WITH STANDARD CLOCKED ELEMENTS},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {6},
        number = {3},
        pages = {79-83},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=148543},
        abstract = {Compelling abatement of timing edges, alleged timing hypothesis, is a applied address for abbreviation voltage for a activity ambit and thusly its adeptness use. Regardless, anticipation of timing blow increases with the voltage ascent and thusly, the goofs have to be adapted with little aeon discipline. Here present an added Razor access by barter cast bend by exhausted bolt, which makes added cutting than others. The proposed action is a low-power and breadth advantageous framework with expedient misstep antidote utilizing little aeon discipline. The commune and ability acceptance are lessened by utilizing this approach. This framework handles the masterminding affair amid exhausted locks application altered non-cover surrendered exhausted alarm developments rather than the accepted individual exhausted alarm flag. So utilizes a yielded cloc alarm generator. Which gives abbreviate put off banderole to snares.},
        keywords = {Low power, Breadth efficient, Timing error, Flip-Flop, Timing Speculation},
        month = {},
        }