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@article{161634,
        author = {Pravallika Pampana and M.Sailaja},
        title = {IMPLEMENTATION OF FPGA-BASED TERNARY CONTENT ADDRESSABLE MEMORY UPDATING MECHANISM BASED ON REVERSIBLE LOGIC},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {10},
        number = {5},
        pages = {237-245},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=161634},
        abstract = {The primary aim of this conceptualization is to devise a highly effective updating mechanism for TCAM (Ternary Content-Addressable Memory). Within this project, we introduce two innovative mechanisms for enhancing FPGA-based TCAMs: the first is an expedited MUX-Update mechanism, while the second is a cost-efficient LUT-Update mechanism. We have developed a 64*36 Gate-Area Effective TCAM for experimental purposes. The MUX-Update mechanism delivers a remarkably swift update latency of W+1 clock cycles, all while utilizing a mere trio of Input/Output (I/O) pins. Meanwhile, the LUT-Update mechanism consistently maintains a low and predictable update latency of just 2 clock cycles, regardless of the TCAM's size, accomplished through the utilization of W I/O pins. Furthermore, to expand upon this concept, we have introduced a novel de-multiplexer design based on reversible gates, aimed at mitigating power constraints.},
        keywords = {Look Up Table, Ternary Content-Addressable Memory, Field Programmable Gate Array, virtual memory management.},
        month = {},
        }