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@article{169562,
        author = {Mara Sandeep Kumar and Thagaram Nithyasruthi and Manda Rahul and V R Seshagiri Rao},
        title = {Built in Self-Test (BIST) for Digital Circuits},
        journal = {International Journal of Innovative Research in Technology},
        year = {2024},
        volume = {11},
        number = {6},
        pages = {1972-1976},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=169562},
        abstract = {Built-In Self-Test (BIST) is a technology that incorporates both hardware and software components, enabling electronic devices to conduct self-assessments. The primary objective of BIST is to develop circuits capable of autonomously testing themselves to identify faults. This study concentrates on improving the fault tolerance of memory testing within the BIST framework. Specifically, we will simulate the MARCH C- algorithm for memory testing on a Xilinx FPGA while implementing mechanisms to detect and correct various memory faults, including Stuck-at faults (SAF) and coupling faults. BIST is primarily used for continuous memory monitoring without interrupting system functionality, functioning as an online testing method. By integrating fault-tolerant strategies, we aim to enhance the robustness and reliability of memory testing processes, with potential applications in RFID integrity verification and avionics systems.},
        keywords = {MARCH C- algorithm, Xilinx, memory faults, fault-tolerant techniques.},
        month = {November},
        }