DESIGN AND ANALYSIS OF COMPRESSOR BASED 16 BIT MULTIPLIER

  • Unique Paper ID: 171981
  • PageNo: 1560-1566
  • Abstract:
  • Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So, in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used, for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently. Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. The compressors are designed using the full adders which provides accurate results in the existing work. The 4:2 and 5:2 compressors are then introduced with delay reduction and ADP reduction. Now the further work concentrated on the implementation of 7:2 Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based multiplier.

Copyright & License

Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{171981,
        author = {K.Radha},
        title = {DESIGN AND ANALYSIS OF COMPRESSOR BASED 16 BIT MULTIPLIER},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {8},
        pages = {1560-1566},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=171981},
        abstract = {Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So, in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used, for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently.
Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. The compressors are designed using the full adders which provides accurate results in the existing work. The 4:2 and 5:2 compressors are then introduced with delay reduction and ADP reduction. Now the further work concentrated on the implementation of 7:2 Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based multiplier.},
        keywords = {Multiplier, Compressors, Half Adder, Full Adder, Area.},
        month = {January},
        }

Cite This Article

K.Radha, (2025). DESIGN AND ANALYSIS OF COMPRESSOR BASED 16 BIT MULTIPLIER. International Journal of Innovative Research in Technology (IJIRT), 11(8), 1560–1566.

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