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@article{175534,
        author = {shamsheer daula},
        title = {Energy-Efficient Contention-Free 25-Transistor Single-Phase Clocked Flip-Flop in 90nm CMOS},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {4209-4216},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=175534},
        abstract = {To significantly enhance energy efficiency in sequential digital circuits, this project will develop an ultralow power true single-phase clocked (TSPC) flip-flop using a novel 25-transistor design, expandable to 29 transistors with a reset function. By eliminating redundant charge and discharge cycles, the flip-flop will drastically reduce power consumption. Transistor-level optimization will be utilized to address floating nodes, ensuring a fully static and contention-free operation within 55 nm CMOS technology. This innovative flip-flop design will be a crucial component in various digital systems, particularly in applications where minimizing power consumption is essential, such as battery-operated devices, IoT systems, and wearable technology. Additionally, it will cater to the growing demand for energy-efficient components in large-scale digital infrastructures like data centers and mobile computing platforms, where optimizing power usage is vital for enhancing overall system performance and sustainability.},
        keywords = {Ultra-low power, Static, Flip-flop, 45 nm technology.},
        month = {April},
        }