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@article{176770,
        author = {Vivek AS and Vaibhav C S and Yashwanth B R and Vivek ks and Veena S},
        title = {DESIGN AND IMPLEMENTATION OF UART USING VERILOG HDL},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {6617-6620},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=176770},
        abstract = {It is a comprehensive study focused on designing and implementing a UART. As a vital component in computer-peripheral communication, the UART enhances the efficiency and accuracy of information transmission. The study begins by exploring the structure, principle, and function of the UART, providing readers with a foundational understanding of its operation. It emphasizes the importance of achieving reliable data transfer, highlighting design considerations for improving transmission accuracy and efficiency.
The study proceeds with the implementation of the UART using Verilog HDL, concentrating on its two primary components: the transmission and reception modules. The transmission module is designed to send binary data bit by bit, while the reception module processes incoming binary codes similarly. To ensure the accuracy of transmitted data, various methods for data confirmation in both modules are implemented. The design is rigorously tested through simulation using Vivado, which validates the functionality and performance of the sending and receiving modules.
In conclusion, the study details the successful design, implementation, and simulation of the UART, achieving efficient and stable full- duplex data transmission and reception. The authors highlight the significance of their work in enhancing the clarity and accuracy of communication systems. The findings contribute valuable insights into UART development, offering a strong foundation for further research and advancements in the field.},
        keywords = {},
        month = {April},
        }