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@article{180736,
        author = {kesarpu sonia and DR .E. Sarva Rameswarudu},
        title = {An Energy Efficient Conditional Boosting Flip -Flop For High Performance Sense Amplification Applications},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {1},
        pages = {2002-2008},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=180736},
        abstract = {One of the major challenges in modern VLSI 
design is power consumption, right up there with space 
and performance. Digital systems rely on the flip-flop. 
In sub-threshold operation, we examine and contrast 
four different flip- flop topologies: IP-DCO, MHLFF, 
CPSFF, and CPFF. Both pulse-triggered and 
conditional approaches are included in these topologies. 
Very low power consumption applications are now 
within reach, thanks to sub threshold technology. One 
advantage of this technique is that it decreases the 
number of power-hungry flip-flops. Compared to a 
strong inversion circuit, a sub threshold circuit 
consumes less power while running at the same 
frequency. Tanner uses 18nm technology in cmos for 
design. We test the flip-flops' power delay, power delay 
product, and average power at a 1V power supply 
voltage and look at them from every perspective.},
        keywords = {Sub Threshold Technology, Flip Flop, Low  Power},
        month = {June},
        }