Design Of A Delay Buffer Using Gated Driver Tree For Low Power Applications

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Ms. V Lakshmi; Racharla Renuka; S. Pushpa; Shaik Shalina; Syed Fayaz; V. Tharun

Design Of A Delay Buffer Using Gated Driver Tree For Low Power Applications

Authors: Ms. V Lakshmi, Racharla Renuka, S. Pushpa, Shaik Shalina, Syed Fayaz, V. Tharun

Unique Paper ID: 180906
Volume: 12
Issue: 1
PageNo: 3437-3441

Keywords: No Keywords Found

Abstract:
This paper presents circuit design of a low power delay buffer. The proposed delay buffer uses new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power.

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ISSN: 2349-6002
Volume: 12
Issue: 1
PageNo: 3437-3441

Design Of A Delay Buffer Using Gated Driver Tree For Low Power Applications

Available:https://ijirt.org/article?manuscript=180906

Impact Factor
8.01 (Year 2024)

UGC Approved
Journal no 47859

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