Design Of A Delay Buffer Using Gated Driver Tree For Low Power Applications

  • Unique Paper ID: 180906
  • Volume: 12
  • Issue: 1
  • PageNo: 3437-3441
  • Abstract:
  • This paper presents circuit design of a low power delay buffer. The proposed delay buffer uses new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power.

Copyright & License

Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{180906,
        author = {Ms. V Lakshmi and Racharla Renuka and S. Pushpa and Shaik Shalina and Syed Fayaz and V. Tharun},
        title = {Design Of A Delay Buffer Using Gated Driver Tree For Low Power Applications},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {1},
        pages = {3437-3441},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=180906},
        abstract = {This paper presents circuit design of a low
power delay buffer. The proposed delay buffer uses 
new techniques to reduce its power consumption. Since 
delay buffers are accessed sequentially, it adopts a 
ring-counter addressing scheme. In the ring counter, 
double-edge-triggered (DET) flip-flops are utilized to 
reduce the operating frequency by half and the C
element gated-clock strategy is proposed. A novel 
gated-clock-driver tree is then applied to further 
reduce the activity along the clock distribution 
network. Moreover, the gated-driver-tree idea is also 
employed in the input and output ports of the memory 
block to decrease their loading, thus saving even more 
power.},
        keywords = {},
        month = {June},
        }

Cite This Article

  • ISSN: 2349-6002
  • Volume: 12
  • Issue: 1
  • PageNo: 3437-3441

Design Of A Delay Buffer Using Gated Driver Tree For Low Power Applications

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