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@article{184334,
        author = {Nisha S and Jalaja S},
        title = {Design and Implementation of AXI4 Master UVC and Slave UVC Using UVM},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {4},
        pages = {970-975},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=184334},
        abstract = {This paper presents design of reusable AXI4 Master Slave Universal Verification Components (UVCs) using the Universal Verification Methodology (UVM) for efficient verification of AXI4 protocol-based System-on-Chip (SoC) design. The UVM structure was selected due to its modularity, scalability, and reusability, making it well-suited for complex protocol verification. The developed UVCs support all AXI4 transaction types, including FIXED, INCR, and WRAP bursts, aligned/unaligned accesses, narrow transfers, and out-of-order transactions. The verification environment integrates sequencers, drivers, monitors, functional coverage, and a scoreboard to ensure protocol compliance and data integrity. Both directed and constrained-random test cases were applied to achieve thorough coverage across diverse scenarios. Simulation results demonstrate higher functional coverage (83%), showing that the proposed verification environment is both robust and efficient. By providing a reusable and scalable AXI4 verification framework, this work contributes to faster verification closure and supports integration into large SoC-level environments. The QuestaSim tool was used for all simulations.},
        keywords = {AMBA, AXI, Functional Coverage, Handshake Mechanism, Master UVC, QuestaSim, Slave UVC, SoC, UVM (Universal Verification Methodology), VIP (Verification IP)},
        month = {September},
        }