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@article{186003,
        author = {Anusha Rao M and Dr Swamy T N},
        title = {HIMCT: Rethinking AI Chip Design with Hybrid In-Memory Compute Tiles},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {5},
        pages = {3574-3580},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=186003},
        abstract = {As artificial intelligence (AI) applications demand increasingly efficient and scalable compute architectures, traditional von Neumann models face critical limitations due to memory bandwidth bottlenecks and high energy consumption. In-memory computing (IMC) using memristive crossbars offers a promising alternative by enabling analog matrix-vector multiplication directly within memory. However, standalone analog architectures lack flexibility, precision, and integration with digital control, limiting their applicability.
This paper presents the Hybrid In-Memory Compute Tile (HIMCT) architecture, a novel AI acceleration paradigm that fuses memristor-based analog computation with digital SRAM buffering, nonlinear processing, and a reconfigurable control scheduler. HIMCT addresses key challenges in existing architectures like ISAAC, PRIME, and PUMA by introducing modular, tile-wise computation, adaptive precision, and dynamic dataflow control. We demonstrate use cases for CNNs and MLPs, highlighting the architecture's ability to reduce energy, improve data reuse, and scale across edge-to-HPC deployments. Initial simulation results validate the computation pipeline, showcasing HIMCT's potential as a practical and reconfigurable compute-in-memory solution for next- generation AI hardware.},
        keywords = {Hybrid In-Memory Computing, AI Accelerator, Compute-in-Memory (CIM), Analog Matrix Multiplication, AI Chips.},
        month = {October},
        }