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@article{186050,
        author = {Shreelakshmi V and Sachin M S},
        title = {Design and Optimization of Ultra-Low-Power AI Accelerator Using Hybrid Memristor-CMOS VLSI Architecture},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {6},
        pages = {7627-7630},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=186050},
        abstract = {We propose a hybrid memristor–CMOS VLSI architecture for an ultra-low-power AI accelerator that leverages memristor crossbars for high-density, in-memory analog multiply-accumulate (MAC) operations together with CMOS digital control, peripheral circuitry, and mixed-signal interfaces. Through device-aware mapping, quantization-aware training, DAC/ADC co-design, and dynamic precision scaling, the proposed design achieves significant gains in energy efficiency and throughput while maintaining comparable accuracy to conventional architectures. Post-layout simulations and system-level analysis demonstrate reductions in energy-per-inference and latency compared to baseline MMSE and Kalman-style digital accelerators. The architecture and optimization strategies provide a practical pathway toward deploying complex AI models at the edge with stringent power budgets},
        keywords = {},
        month = {January},
        }