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@article{188418,
        author = {shipra garg and Dr. Pragati Sharma},
        title = {Full-Swing Local Bitline SRAM FinFET Technology: A Review},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {7},
        pages = {1946-1952},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=188418},
        abstract = {The earlier average-8T static RAM (SRAM) design offers a competitive cell area and eliminates the need for a write-back mechanism. In this architecture, a full-swing local bitline (BL) connected to the read buffer’s gate can normally be produced by applying a boosted wordline (WL) voltage. However, when implemented in more advanced technologies such as a 22-nm FinFET process, where threshold-voltage variation is significant a boosted WL voltage is not feasible because it negatively affects read stability. As a result, the local BL cannot reach a full swing, and the read buffer’s gate is not driven by the full supply voltage (VDD), which leads to a substantial increase in read delay.To address this limitation, this paper introduces a differential SRAM architecture capable of generating a full-swing local BL. This is achieved by incorporating cross-coupled pMOS devices, allowing the read buffer’s gate to be driven by the full VDD without relying on WL boosting. Several multi-bit configurations of the proposed architecture are evaluated with respect to minimum operating voltage and area efficiency. The version storing four bits per block demonstrates a minimum operating voltage of 0.42 V and achieves a read delay reduction by a factor of 62.6 compared to the average-8T SRAM fabricated in 22-nm FinFET technology.},
        keywords = {Bit-interleaving, FinFET, low-voltage operation, static random-access memory (SRAM).},
        month = {December},
        }