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@article{192322,
        author = {KALAKURASA RAKESH and Moturi Satyanarayana},
        title = {An Efficient FPGA Based Hardware Trojan Detection Model Using Partial Reconfiguration Procedure},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {9},
        pages = {1447-1455},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=192322},
        abstract = {The use of Field Programmable Gate Array (FPGA) became a fundamental device in modern system on chip (SoC) designs. Recent reports about hardware Trojan attacks on secure system are on upswing due to the outsourced designs with third-party IP cores. The globalization of hardware supply from manufacturers reduces NRE cost but increases security challenges in the form of Hardware Trojans which may put the end user confidential date at risk. The necessity to detect Hardware Trojan by traditional methods like Trojan free gold chips always faces scalability limitations by relying solely on chip sequences. The recoverable methods are mostly based on the identification of the Trojan presence at behavioral level. In this paper a new technique based on partial reconfiguration procedure was introduced for the Trojan insertion and to detect it without a golden chip. Experimental data obtained from the PYNQ Z2 board shows that this work based on dynamic partial reconfiguration uses lowest resource utilization and the detection accuracy is noteworthy.},
        keywords = {Third-party IP cores, Dynamic Partial Reconfiguration (DPR), Hardware Trojan and Reconfigurable system.},
        month = {February},
        }