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@article{192554,
        author = {Dr. Tammisetti Ashok and Koliki Jyothika and Pakala Naga Venkata Rajesh and Motamarri Neeraja Devi and Koyya Maanas Reddy and Pilli Praveen Raju},
        title = {Design and Verification of a Parameterized Asynchronous FIFO Using Gray Code Synchronization},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {9},
        pages = {2926-2935},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=192554},
        abstract = {Asynchronous First-In First-Out (FIFO) buffers are widely used in digital systems to enable reliable data transfer between independent clock domains. However, improper handling of clock domain crossing (CDC) may lead to data corruption and metastability issues. This paper presents the design, implementation, and verification of a parameterized asynchronous FIFO architecture employing gray code counters and dual flip-flop synchronizers to ensure safe pointer synchronization across clock domains.
The proposed FIFO supports independent read and write clocks and incorporates robust full and empty detection mechanisms using additional pointer bits to distinguish wrapping conditions. Separate read and write pointer handler modules operate in their respective clock domains, while synchronized pointer exchange is achieved using two-stage flip-flop synchronizers. The FIFO memory is implemented as a dual-port RAM, allowing concur-rent read and write operations without clock interference.
Functional verification is carried out using a comprehensive testbench that validates correct data storage and retrieval, as well as proper handling of boundary conditions such as FIFO full and empty states. Simulation results confirm reliable operation under asynchronous clock conditions with differing clock frequencies.
The presented design is modular, scalable, and parameterized, making it suitable for FPGA- and ASIC-based systems requiring safe clock domain crossing. While functional correctness is verified through simulation, the design also adheres to established CDC mitigation techniques, ensuring robustness in practical hardware implementations.},
        keywords = {Asynchronous FIFO, Clock Domain Crossing, Gray Code Counter, FPGA, Metastability, Dual-Port Memory},
        month = {February},
        }