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@article{195941,
        author = {Karthigaa S and Nisanth T and Gangiesh S and Vallisree S},
        title = {Comparative Performance Analysis of Single-Stage and Pipelined RISC-V Processors on FPGA},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {2264-2270},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=195941},
        abstract = {This paper presents a comparative performance analysis of two RISC-V processor architectures: a single-stage processor and a five-stage pipelined processor. Leveraging the open-source and modular nature of the RISC-V instruction set architecture, both processors were designed and implemented using Verilog HDL. The single-stage architecture offers design simplicity by executing one instruction per clock cycle, whereas the pipelined architecture divides instruction execution into five stages to improve instruction throughput. C test programs were compiled into RISC-V machine code using a cross-compilation toolchain and converted into Intel HEX (.hex) format for loading into the instruction memory. Both architectures were simulated and synthesized on an FPGA to evaluate key performance metrics such as clock period, resource utilization, and execution speed. The results show that the pipelined processor achieves a maximum operating frequency of 158.48 MHz, compared to 51.07 MHz for the single-stage design, resulting in a speedup of up to 3.1 times for long instruction sequences. This study highlights the trade-off between architectural simplicity and execution throughput and demonstrates the effectiveness of RISC-V as a flexible platform for processor design.},
        keywords = {RISC-V, Pipelining, Single-Stage Processor, FPGA (Field-Programmable Gate Array), Verilog HDL, Instruction Set Architecture (ISA), Hazard Mitigation.},
        month = {April},
        }