Design and Verification of a Finite State Machine-Based Watchdog Controller for FPGA-Driven Process Supervision

Copyright & License

Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{196286,
        author = {Senthilmurugan S. and Abishek Prasad C. S. and Govindaraj P. and Guru Aakash P. S.},
        title = {Design and Verification of a Finite State Machine-Based Watchdog Controller for FPGA-Driven Process Supervision},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {3632-3635},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=196286},
        abstract = {},
        keywords = {FPGA, Finite State Machine, Watchdog Controller, Process Supervision, Zynq-7000, Hardware–Software Co-Design, Vivado, Embedded Systems.},
        month = {April},
        }

Cite This Article

S., S., & S., A. P. C., & P., G., & S., G. A. P. (2026). Design and Verification of a Finite State Machine-Based Watchdog Controller for FPGA-Driven Process Supervision. International Journal of Innovative Research in Technology (IJIRT), 12(11), 3632–3635.

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