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@article{196662,
        author = {Tamil Selvan R and Swamy Nathan G and Sibi Raj V V and Vikkass Shethra Balan M},
        title = {SRAM CIM-Based Matrix Multiplication for Edge Intelligence},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {3895-3900},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=196662},
        abstract = {Static Random Access Memory (SRAM) is a key component in modern digital systems due to its high speed, low latency, and reliability. With the rapid advancement of Artificial Intelligence (AI), Internet of Things (IoT), and edge computing systems, there is an increasing demand for efficient memory architectures that can support both storage and computation. Conventional systems suffer from high energy consumption and latency due to frequent data transfer between memory and processor. This paper presents the design and implementation of a 4×4 SRAM memory array using a conventional 6-transistor (6T) SRAM cell in the Cadence Virtuoso environment. The proposed design integrates essential peripheral circuits such as pre-charge circuits, write drivers, sense amplifiers, and address decoders to ensure efficient operation. Detailed simulation results demonstrate successful read, write, and hold operations with stable performance. Furthermore, this work explores the potential of extending SRAM toward Compute-in-Memory (CIM) architectures, enabling vector–matrix multiplication directly within memory. This significantly reduces data movement and improves computational efficiency. The proposed design serves as a foundation for future AI-based and edge computing applications.},
        keywords = {SRAM, CIM, Cadence Virtuoso, 6T Cell, Edge Computing, Matrix Multiplication},
        month = {April},
        }