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@article{198527,
        author = {Harshada Dalvi and Pravin Bhangare and Vaishnavi Bauchkar and Akhil Masurkar},
        title = {Design and Performance Evaluation of 2-Stage OPAMP with Nulling Resistor and Miller Capacitance},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {13247-13258},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198527},
        abstract = {Frequency compensation is one of the most critical steps in designing a stable CMOS operational amplifier, and this work takes a close look at how two different compensation strategies perform in practice. Specifically, we compare conventional Miller compensation against an enhanced version that adds a nulling resistor in series with the Miller capacitor, both implemented in a two-stage CMOS op-amp using 180 nm CMOS technology. Simulations were carried out in Cadence Virtuoso under a 1.8 V supply with a 2 pF load. The results show that the nulling-resistor design achieves a phase margin of 77.43°—a substantial improvement over the 45.86° seen in the basic Miller design—while keeping the DC gain fixed at 70 dB and CMRR around 73.6 dB. The gain-bandwidth product also goes up, from 75 MHz to 83 MHz. Taken together, these numbers confirm that the series resistor eliminates the troublesome right-half-plane zero that the Miller capacitor would otherwise introduce, and that this translates directly into better closed-loop stability at virtually no extra power cost.},
        keywords = {Two-stage op-amp, Miller compensation, Nulling resistor, Phase margin, CMRR, Gain-bandwidth product, CMOS analog design.},
        month = {April},
        }